1. Field of the Invention
The present invention relates to a system and a method for offsetting the input voltage unbalance of condenser benches in multilevel inverters or similar devices.
2. Description of the Related Art
The use is known and has been common for some time of electronic apparatus so-called “inverters” suitable for converting a direct input current into an alternate output current.
The applications of inverters are numerous and go, e.g., from the use in UPS units for the conversion of direct current from a power battery, to use in industry for adjusting the speed of electric motors or, again, to use for the conversion of electricity coming from production plants such as, e.g., photovoltaic plants, before introduction into the power distribution network.
A particular type of inverter is the multilevel inverter, so-called NPC (Neutral Point Clamped), which is able to supply more than two levels of power voltage at output so as to generate a wave shape as close as possible to a sinusoid shape. By way of example, FIG. 1 shows the general diagram of a three-phase, triple-level NPC inverter.
At the input to an NPC inverter, several condensers are commonly used in series to split up the total power voltage and create the voltage levels required to generate the output voltage.
The inverter of FIG. 1, in particular, has an input branch composed of two condensers C of the same capacity in series the one with the other and associated with a power voltage source Vdc in correspondence to a terminal with positive power voltage Vdc+, to a terminal with negative power voltage Vdc− and to a neutral point NP (Neutral Point) between the two condensers C.
The inverter shown in FIG. 1 comprises three electronic power switching units, such as Mosfet, IGBT or similar devices, indicated by the references Sa1 Sb1 Sc1 Sd1 Sa2 Sb2 Sc2 Sd2 and Sa3 Sb3 Sc3 Sd3, which are suitably connected together on three branches, one for each phase f1, f2 and f3.
The inverter also comprises three pairs of diodes, indicated in FIG. 1 by the references Da1 and Db1, Da2 and Db2, Da3 and Db3 respectively.
With reference to the branch relating to the phase f1, e.g., the diodes Da1 and Db1 are arranged in series the one with the other and connect the neutral point NP to the connection point between the switches Sa1 and Sb1 and to the connection point between the switches Sc1 and Sd1 respectively.
The diodes Da2, Db2, and Db3 are similarly connected with the branches relating to the phases f2 and f3.
By commanding the closing of the switches Sa1 Sb1 Sc1 Sd1, Sa2 Sb2 Sc2 and Sd2 and Sa3 Sb3 Sc3 Sd3 each of the phases can be connected to the positive of the voltage Vdc+, to the negative of the voltage Vdc− and to the node NP (Neutral Point) with intermediate voltage compared to Vdc+ and Vdc−.
The quick switching of the switches between the possible configurations is performed by means of suitable modulation techniques, so as to obtain an alternate voltage and output current on the three phases, starting with the direct power voltage Vdc.
The operation of these multilevel inverters of NPC type, single or multiphase, does however have a number of drawbacks.
In particular, during operation, a voltage unbalance can occur on the benches of condensers C at its input, conventionally known as “DC bus voltages”.
The condensers C, in fact, can charge and discharge to a different extent according to the conduction time window of the different components, thereby producing output voltages of different amplitude.
The equalization of the CD bus voltages during inverter operation can be performed using different systems and methods of known type.
A first known method, e.g., envisages the use of electronic circuits in addition to the inverter, suitable for balancing, moment per moment, the voltage at the heads of the two condensers C on the input branch.
Such electronic circuits of known type, however, are not without their drawbacks.
In fact, these electronic circuits are of the dissipative type, because the equalization is partially achieved by dissipating the excess energy present on one of the two condensers C and loading the other of the condensers C through the power voltage source Vdc at input.
Furthermore, this equalization method requires the insertion of additional circuit elements which increase the costs and the overall complexity of the system. A second equalization method of known type, on the other hand, envisages the use of suitable methods of modulation of the inverter switches.
These methods however are not without drawbacks either.
Their use, in fact, considerably increases the complexity of the system because, in particular when three-phase converters are used, they can only be implemented by means of the coordinated operation of the three groups of inverters on the three output branches.
A further known equalization method envisages the use of two independent power voltage sources, realizable by means of two distinct DC supply units or by means of a so-called “symmetric booster”.
This method too however implies a greater complexity and a higher cost of the system.
Finally, another equalization method of known type envisages the supply of a direct mains current able to unbalance the powers absorbed by the two condensers C, thus permitting the equalization of the two DC bus power voltages.
This equalization method also has problems tied in particular to the applicable standards regulating the connection to the power mains network, which indicate very stringent limits for the supply of a direct component in the mains.
The document JP 07 079574 discloses a control circuit for three-level inverter provided with means for adding an harmonic component of the fundamental frequency of the inverter to the output voltage of each phase of the inverter and means for detecting the voltage unbalance of the DC bus voltage and for deciding the amplitude of the harmonic component to be added to the output.
The document U.S. Pat. No. 7,495,938 discloses three-level inverter and rectifier power conversion systems and space vector modulation controls having even-order harmonic elimination for neutral voltage balancing with a predefined vector switching sequences for half-wave symmetry in open loop system operation.
The document U.S. Pat. No. 6,842,354 discloses a power converter including a DC to AC inverter wherein to compensate for a voltage imbalance across the capacitors, an imbalance compensation coefficient is derived from the difference in voltages across the first and second capacitors of the DC bus voltage and the imbalance compensation coefficient is employed to adjust the width of the output pulses so as to charge and discharge the capacitors to correct the imbalance.
The document identified with the NPL (Non-Patent Literature) reference number XP 010042112, titled “DSP based space vector PWM for three-level inverter with DC-link voltage balancing” (IECON, NE, vol. CONF. 17, 28 Oct. 1991) discloses a PWM method for three-level inverter wherein each voltage vector on space vector plane is classified in relation to charging discharging action of DC capacitors and wherein a modulation method is defined based on the voltage vector selection principle.